1. Field of the Invention
The present invention relates generally to a semiconductor device and method of fabricating the same. In particular, the present invention relates to a semiconductor device with a pull backed gate structure and a method of fabricating the same.
2. Description of the Prior Art
In recent years, as various kinds of consumer electronic products are constantly improved and miniaturized, the size of semiconductor components have reduced accordingly, in order to meet requirements of high integration, high performance, and low power consumption.
With the trend in the industry being towards scaling down the size of the metal oxide semiconductor transistors (MOS), three-dimensional or non-planar transistor technology, such as fin field effect transistor technology (Fin FET) has been developed to replace planar MOS transistors. The three-dimensional structure of a fin FET increases the overlapping area between the gate and the fin structure of the silicon substrate, the channel region is therefore accordingly more effectively controlled. The drain-induced barrier lowering (DIBL) effect and the short channel effect are therefore reduced. The channel region is also longer for an equivalent gate length, thus the current between the source and the drain is increased. In addition, the threshold voltage of the fin FET can be controlled by adjusting the work function of the gate.
In conventional processes for fabricating fin FET devices, the sidewalls of the gate and fin structures are covered with a spacer. The material of said spacer tends to remain on the sidewalls of the fin structure, and the poor gap filling capacity makes it hard to fill the recess or the trench structure during the formation of said spacer. Furthermore, the presence of a spacer will hinder the following ion implantation process for forming lightly doped drain (LDD), because the dopants will be blocked by the spacer and will be hard to be implanted in the sidewalls of the fin structures. Thus, the gate device formed by this conventional process may induce a large electric field gradient and impact the electrical properties of the gate device.
Accordingly, the present invention is directed to improve the conventional forming process for fin FET devices, in order to further enhance the performance of the devices.